1. Technical Field
The present invention is directed generally to a lead structure for use in semiconductor device packaging, and more particularly, to a lead or finger structure for a semiconductor device packaged in a tape carrier system.
2. Related Technical Art
FIGS. 24 and 25 show how leads or fingers are mounted on a semiconductor integrated substrate which is to be packaged in a conventional tape carrier system. In this semiconductor device, a device hole 15 is formed at the center of an elongated polyimide tape 10 including sprocket holes 11. An IC chip 20 is inserted in the device hole 15. Electrodes 21 of the chip 20 are connected to one end of fingers 30, i.e. inner lead parts 31 formed on the surface of the polyimide tape 10. Tips of outer lead parts 32, viz., the other ends of the fingers 30, are cut outer lead holes 18 and connected to electrodes of the substrate.
A method of manufacturing the above-described tape carrier is demonstrated in FIGS. 26A-26B. The following is a general description of the respective steps.
Step 1: The device hole 15 in which the IC chip is mounted is punched out at the center of the polyimide tape 10 having its upper surface formed with a bonding layer 12. The sprocket holes 11 and the outer lead holes 18 are punched out along the circumference thereof (FIG. 26A. PA0 Step 2: A copper foil 13 is laminated on the bonding layer 12 (FIG. 26B. PA0 Step 3: A resist 14 is coated onto the copper foil 13, and thereafter the resist 14 is removed while the finger parts are left using lithography (FIG. 26C). PA0 Step 4: A protective resist 16 is coated on a rear face of the polyimide tape 10 to prevent etching from the rear face (FIG. 26D). PA0 Step 5: Etching effected on the polyimide tape 10 to form the finger parts (FIG. 26E). PA0 Step 6: The resists 14 and 16 are removed.
Considering an etching limit, decline in lead strength, or alignment accuracy, the pitch of the fingers formed by the above-mentioned method is limited to approximately 80 Pm. On the other hand, with advancement toward a hyperfine semiconductor integrated circuit and improvement in integration rates thereof, inputs and outputs are increased, and the circuit is multi-pinned. Under such circumstances, electrode density on the semiconductor integrated substrate also increases. Hence, fingers are required which are capable of corresponding to the high density of electrodes and causing less inconvenience such as deformation and the like.
The circuit substrate mounted with the semiconductor circuit is also required to be miniaturized. It is, therefore, required that a multiplicity of integrated circuits be mounted in a limited area. The conventional finger structure, however, presents difficulty in reducing the area occupied by the fingers. This is because the area occupied by the fingers increases with the advancement of multi-pinning. Besides, the conventional finger shows a one-to-one correspondence to the integrated circuit, whereby a wide area is needed for the fingers for integrated circuits.
The present invention, which has been made in the light of such problems, aims at reducing the area occupied by the fingers by cubically arranging the fingers, providing a construction capable of corresponding to the multi-pinned integrated circuit, and further improving the packaging density by simultaneously mounting the plurality of integrated circuits.
3. Disclosure of the Invention
To obviate the problems described above, in a semiconductor device according to this invention, a multi-layered conductive pattern unit including at least a single insulating layer and plural conductive layers is mounted on a semiconductor integrated substrate. Formed in a part of the conductive layer is a wiring pattern having its one end connected to electrodes of the semiconductor substrate and the other end extending outside. The cubic wiring pattern is thus configured.
The conductive pattern unit including the cubically configured wiring pattern is mounted on the semiconductor integrated substrate. The integrated substrate is connected to the wiring pattern of a single layer of the multi-layered structure. Another integrated substrate is connected to the wiring pattern of another layer. Namely, a plurality of semiconductor integrated substrates are mounted with this conductive pattern unit being sandwiched in between. These substrates are also connectable through a pattern formed in the conductive layers within the multi-layered conductive pattern unit.
In a semiconductor device comprising a film-like flexible substrate formed with a device hole and at least one semiconductor integrated substrate mounted in the device hole, the same conductive pattern unit as the above is mounted on this semiconductor integrated substrate.
When the wiring patterns are formed in a plurality of conductive layers of the conductive pattern unit, a plurality of wiring patterns can be laminated by use of a mask pattern assuming the same configuration. When single-layered electrode strings are formed, the connections to the circuit substrate are facilitated by the other ends, extending outside, of the wiring patterns.
Besides, it is effective to form an electrification path in a thickness-wise direction of the conductive pattern unit. The electrodes of the semiconductor substrate are connectable to the wiring pattern through this electrification path. This electrification path is provided in the form of a through-hole or a bump.
The plurality of layers constituting the conductive pattern unit are connectable to each other through the electrification path formed in the thickness-wise direction of the conductive pattern unit. Further, the multilayered wiring patterns can be connected to a multiplicity of electrodes arranged in a plurality of rows on the integrated substrate and the packaging substrate as well.
The insulating layer may be formed of polyimide. A polyimide tape is usable as the flexible substrate given above.
One method of manufacturing such a semiconductor device comprises the step of forming a conductor pattern unit on a flexible substrate by photolithography. In this conductor pattern forming step, an insulating layer is formed based on a roll coat method.